#include <inttypes.h>

#ifndef	_DDS_REG_DEFINE
#define		_DDS_REG_DEFINE
/***************************************/
/*                                                                 */
/*             AD9913 registers definition             */
/*                                                                 */
/***************************************/

/*Register Addresses For Serial Operation*/
#define		_CFR1_ADDR				((regAddr_t)0x00)	//Address:Control Function Register 1
#define		_CFR2_ADDR				((regAddr_t)0x01)	//Address:Control Function Register 2
#define		_DACC_ADDR			((regAddr_t)0x02)	//Address:DAC Control Register
#define		_FTW_ADDR				((regAddr_t)0x03)	//Address:Frequency Tuning Word
#define		_POW_ADDR				((regAddr_t)0x04)	//Address:Phase Offset Word
#define		_LSPARA_ADDR			((regAddr_t)0x06)	//Address:Linear Sweep Parameter Registe
#define		_LSDPARA_ADDR			((regAddr_t)0x07)	//Address:Linear Sweep Delta Parameter Register
#define		_LSRA_ADDR				((regAddr_t)0x08)	//Address:Linear Sweep Ramp Rate Register
#define		_PRF0_ADDR				((regAddr_t)0x09)	//Address:Profile 0
#define		_PRF1_ADDR				((regAddr_t)0x0A)	//Address:Profile 1
#define		_PRF2_ADDR				((regAddr_t)0x0B)	//Address:Profile 2
#define		_PRF3_ADDR				((regAddr_t)0x0C)	//Address:Profile 3
#define		_PRF4_ADDR				((regAddr_t)0x0D)	//Address:Profile 4
#define		_PRF5_ADDR				((regAddr_t)0x0E)	//Address:Profile 5
#define		_PRF6_ADDR				((regAddr_t)0x0F)	//Address:Profile 6
#define		_PRF7_ADDR				((regAddr_t)0x10)	//Address:Profile 7

/*Bit Base Addresses In CFR1*/
#define		_SIN_OUT_BA				ctrlFuncReg1.regByt1	//In Register Base Address:Enable Sine Output
#define		_AUTCLR_PHS_ACC_BA		ctrlFuncReg1.regByt1	//In Register Base Address:Autoclear Phase Accumulator
#define		_AUTCLR_AUX_ACC_BA		ctrlFuncReg1.regByt1	//In Register Base Address:Autoclear Auxiliary Accumulator
#define		_LOAD_SRR_BA				ctrlFuncReg1.regByt1	//In Register Base Address:Load Sweep Rate Register at IO_UPDATE
#define		_CLKIN_PWRDWN_BA			ctrlFuncReg1.regByt1	//In Register Base Address:Clock Input Power-Down
#define		_DAC_PWRDWN_BA			ctrlFuncReg1.regByt1	//In Register Base Address:DAC Power-Down
#define		_DIGICORE_PWRDWN_BA		ctrlFuncReg1.regByt1	//In Register Base Address:Digital Core Power-Down
#define		_EXT_PWRDWN_BA			ctrlFuncReg1.regByt1	//In Register Base Address:External Power-Down Mode
#define		_LS_NDWELL_BA				ctrlFuncReg1.regByt2	//In Register Base Address:Linear Sweep No_DWell Active
#define		_LS_STAT_TRG_BA			ctrlFuncReg1.regByt2	//In Register Base Address:Linear Sweep State Trigger Active
#define		_DC_OUT_BA				ctrlFuncReg1.regByt2	//In Register Base Address:DC Output Active
#define		_AUX_ACC_BA				ctrlFuncReg1.regByt2	//In Register Base Address:Auxiliary Accumulator Enable
#define		_DESTI_BA					ctrlFuncReg1.regByt2	//In Register Base Address:Destination,Defining The Usage Of Auxiliary Accumulator,Two Bits
#define		_CLR_PHS_ACC_BA			ctrlFuncReg1.regByt2	//In Register Base Address:Clear Phase Accumulator
#define		_CLR_AUX_ACC_BA			ctrlFuncReg1.regByt2	//In Register Base Address:Clear Auxiliary Accumulator
#define		_DIRSWT_MODE_BA			ctrlFuncReg1.regByt3	//In Register Base Address:Direct Switch Mode Active
#define		_SYNC_CLK_BA				ctrlFuncReg1.regByt3	//In Register Base Address:Sync Clock Disable
#define		_INT_PROFILE_CTRL_BA		ctrlFuncReg1.regByt3	//In Register Base Address:Internal Profile Control,Three Bits
#define		_LSB_FIRST_BA				ctrlFuncReg1.regByt3	//In Register Base Address:LSB First Control
#define		_MPL_DELAY_BA				ctrlFuncReg1.regByt4	//In Register Base Address:Match PipeLine Delay Active
#define		_USE_INT_PROFILE_BA		ctrlFuncReg1.regByt4	//In Register Base Address:Use Internal Profile
#define		_MDU_BA					ctrlFuncReg1.regByt4	//In Register Base Address:Enable Modulus

/*Bit Offset Addresses In CFR1*/
#define		_SIN_OUT_OFS				((regBitOfs_t)0x01)	//In Register Offset Address:Enable Sine Output
#define		_AUTCLR_PHS_ACC_OFS		((regBitOfs_t)0x02)	//In Register Offset Address:Autoclear Phase Accumulator
#define		_AUTCLR_AUX_ACC_OFS		((regBitOfs_t)0x04)	//In Register Offset Address:Autoclear Auxiliary Accumulator
#define		_LOAD_SRR_OFS				((regBitOfs_t)0x08)	//In Register Offset Address:Load Sweep Rate Register at IO_UPDATE
#define		_CLKIN_PWRDWN_OFS		((regBitOfs_t)0x10)	//In Register Offset Address:Clock Input Power-Down
#define		_DAC_PWRDWN_OFS			((regBitOfs_t)0x20)	//In Register Offset Address:DAC Power-Down
#define		_DIGICORE_PWRDWN_OFS	((regBitOfs_t)0x40)	//In Register Offset Address:Digital Core Power-Down
#define		_EXT_PWRDWN_OFS			((regBitOfs_t)0x80)	//In Register Offset Address:External Power-Down Mode
#define		_LS_NDWELL_OFS			((regBitOfs_t)0x01)	//In Register Offset Address:Linear Sweep No_DWell Active
#define		_LS_STAT_TRG_OFS			((regBitOfs_t)0x02)	//In Register Offset Address:Linear Sweep State Trigger Active
#define		_DC_OUT_OFS				((regBitOfs_t)0x04)	//In Register Offset Address:DC Output Active
#define		_AUX_ACC_OFS				((regBitOfs_t)0x08)	//In Register Offset Address:Auxiliary Accumulator Enable
#define		_DESTI_OFS					((regBitOfs_t)0x30)	//In Register Offset Address:Destination,Defining The Usage Of Auxiliary Accumulator,Two Bits
#define		_CLR_PHS_ACC_OFS			((regBitOfs_t)0x40)	//In Register Offset Address:Clear Phase Accumulator
#define		_CLR_AUX_ACC_OFS			((regBitOfs_t)0x80)	//In Register Offset Address:Clear Auxiliary Accumulator
#define		_DIRSWT_MODE_OFS			((regBitOfs_t)0x01)	//In Register Offset Address:Direct Switch Mode Active
#define		_SYNC_CLK_OFS				((regBitOfs_t)0x08)	//In Register Offset Address:Sync Clock Disable
#define		_INT_PROFILE_CTRL_OFS		((regBitOfs_t)0x70)	//In Register Offset Address:Internal Profile Control,Three Bits
#define		_LSB_FIRST_OFS				((regBitOfs_t)0x80)	//In Register Offset Address:LSB First Control
#define		_MPL_DELAY_OFS			((regBitOfs_t)0x04)	//In Register Offset Address:Match PipeLine Delay Active
#define		_USE_INT_PROFILE_OFS		((regBitOfs_t)0x08)	//In Register Offset Address:Use Internal Profile
#define		_MDU_OFS					((regBitOfs_t)0x10)	//In Register Offset Address:Enable Modulus

/*Bit Settings In CFR1*/
#define		EN_SIN_OUT					((regBitVal_t)0x01)		//Bit Set:The Angle-To-Amplitude Conversion Logic employs a Sine Function.
#define		DIS_SIN_OUT				((regBitVal_t)0x00)		//Bit Set:The Angle-To-Amplitude Conversion Logic employs a Cosine Function.
#define		EN_AUTCLR_PHS_ACC		((regBitVal_t)0x02)		//Bit Set:The Phase Accumulator is synchronously cleared for one cycle upon recept of the IO_UPDATE sequence indicator.
#define		DIS_AUTCLR_PHS_ACC		((regBitVal_t)0x00)		//Bit Set:Phase Accumulator is normally operated.
#define		EN_AUTCLR_AUX_ACC		((regBitVal_t)0x04)		//Bit Set:The Auxiliary Accumulator is synchronously cleared(zero is loaded) for one cycle upon recept of the IO_UPDATE sequence indicator.
#define		DIS_AUTCLR_AUX_ACC		((regBitVal_t)0x00)		//Bit Set:Auxiliary Acculator is normally operated.
#define		EN_LOAD_SRR				((regBitVal_t)0x08)		//Bit Set:The Ramp Rate Timer is interrupted immediately upon the assertion of IO_UPDATE and the value is loaded.
#define		DIS_LOAD_SRR				((regBitVal_t)0x00)		//Bit Set:Every time the Linear Sweep Rate Register is updated ,the Ramp Rate Timer keeps its operation until it times out and then loads the value.
#define		EN_CLKIN_PWRDWN			((regBitVal_t)0x10)		//Bit Set:Shut down all Clock Generation including the system clock signal going into the Digital Section.
#define		DIS_CLKIN_PWRDWN			((regBitVal_t)0x00)		//Bit Set:Normal Operation.
#define		EN_DAC_PWRDWN			((regBitVal_t)0x20)		//Bit Set:The DAC is disabled and is in its lowest power dissipation state.
#define		DIS_DAC_PWRDWN			((regBitVal_t)0x00)		//Bit Set:The DAC is enabled for operation.
#define		EN_DIGICORE_PWRDWN		((regBitVal_t)0x40)		//Bit Set:The Digital Core is disabled and is in a low power idssipation state.
#define		DIS_DIGICORE_PWRDWN		((regBitVal_t)0x00)		//Bit Set:The Digital Core is enabled for operation.
#define		FULDWN_EXT_PWRDWN		((regBitVal_t)0x80)		//Bit Set:The External Power-Down Mode selected is the Full Powe-Down Mode.
#define		FSTREC_EXT_PWRDWN		((regBitVal_t)0x00)		//Bit Set:The External Power-Down Mode selected is the Fast recovery Power-Down Mode.
#define		EN_LS_NDWELL				((regBitVal_t)0x01)		//Bit Set:When a Sweep is completed, the device reverts to the initial state.
#define		DIS_LS_NDWELL				((regBitVal_t)0x00)		//Bit Set:When a Sweep is completed, the device holds at the final state.
#define		EN_LS_STAT_TRG			((regBitVal_t)0x02)		//Bit Set:State Triggered Mode active.
#define		DIS_LS_STAT_TRG			((regBitVal_t)0x00)		//Bit Set:Edge Triggered Mode active.
#define		EN_DC_OUT					((regBitVal_t)0x04)		//Bit Set:The output of the DAC is driven to full-scale and the DDS output is disabled.
#define		DIS_DC_OUT					((regBitVal_t)0x00)		//Bit Set:Normal operating state.
#define		EN_AUX_ACC				((regBitVal_t)0x08)		//Bit Set:Auxiliary Accumulator is active.
#define		DIS_AUX_ACC				((regBitVal_t)0x00)		//Bit Set:Auxiliary Accumulator is inactive.
#define		PHS_DESTI_AUX_ACC			((regBitVal_t)0x10)		//Bit Set:In Direct Switch Mode,use this setting for PSK.In Linear Sweep Mode,the Auxiliary Accumulator is used for phase sweeping.
#define		FREQ_DESTI_AUX_ACC		((regBitVal_t)0x00)		//Bit Set:In Direct Switch Mode,use this for FSK.In Linear Sweep Mode, the Auxiliary Accumulator is used for frequency sweeping.Must be setted in Porgrammable Modulus Mode.
#define		EN_CLR_PHS_ACC			((regBitVal_t)0x40)		//Bit Set:Asychronous, static reset of the DDS Phase Accumulator.
#define		DIS_CLR_PHS_ACC			((regBitVal_t)0x00)		//Bit Set:Normal operation of the DDS Phase Accumulator(default).
#define		EN_CLR_AUX_ACC			((regBitVal_t)0x80)		//Bit Set:Asychronous,static reset of the Auxiliary Accumulator.The Ramp Accumulator remains reset as long as this bit remains set.This bit is synchronized with either an I/O Update or a profile change and the next rising edge of SYNC_CLK.
#define		DIS_CLR_AUX_ACC			((regBitVal_t)0x00)		//Bit Set:Normal operation of the Auxiliary Accumulator(default).
#define		EN_DIRSWT_MODE			((regBitVal_t)0x01)		//Bit Set:Direct Switch Mode is enabled.
#define		DIS_DIRSWT_MODE			((regBitVal_t)0x00)		//Bit Set:Direct Switch Mode is disabled.
#define		EN_SYNC_CLK				((regBitVal_t)0x00)		//Bit Set:The SYNC_CLK pin is active.
#define		DIS_SYNC_CLK				((regBitVal_t)0x08)		//Bit Set:The SYNC_CLK pin assumes a static logic 0 state(disable).
#define		USE_PROFILE0				((regBitVal_t)0x00)		//Bit Set:Effective only if the Bit 27 of CFR1 equals 1.Use Profile 0.
#define		USE_PROFILE1				((regBitVal_t)0x10)		//Bit Set:Effective only if the Bit 27 of CFR1 equals 1.Use Profile 1.
#define		USE_PROFILE2				((regBitVal_t)0x20)		//Bit Set:Effective only if the Bit 27 of CFR1 equals 1.Use Profile 2.
#define		USE_PROFILE3				((regBitVal_t)0x30)		//Bit Set:Effective only if the Bit 27 of CFR1 equals 1.Use Profile 3.
#define		USE_PROFILE4				((regBitVal_t)0x40)		//Bit Set:Effective only if the Bit 27 of CFR1 equals 1.Use Profile 4.
#define 		USE_PROFILE5				((regBitVal_t)0x50)		//Bit Set:Effective only if the Bit 27 of CFR1 equals 1.Use Profile 5.
#define		USE_PROFILE6				((regBitVal_t)0x60)		//Bit Set:Effective only if the Bit 27 of CFR1 equals 1.Use Profile 6.
#define		USE_PROFILE7				((regBitVal_t)0x70)		//Bit Set:Effective only if the Bit 27 of CFR1 equals 1.Use Profile 7.
#define		EN_LSB_FIRST				((regBitVal_t)0x80)		//Bit Set:LSB First format is used.
#define		DIS_LSB_FIRST				((regBitVal_t)0x00)		//Bit Set:MSB First format is used.
#define		EN_MPL_DELAY				((regBitVal_t)0x04)		//Bit Set:The latency across the Auxiliary Accumulator, the Phase Offset Word, and Phase Accumulator are matched.
#define		DIS_MPL_DELAY				((regBitVal_t)0x00)		//Bit Set:The latency across the Auxiliary Accumulator, the Phase Offset Word, and Phase Accumulator are matched.
#define		EN_USE_INT_PROFILE		((regBitVal_t)0x08)		//Bit Set:Profiles are controlled by CFR1[22:20]
#define		DIS_USE_INT_PROFILE		((regBitVal_t)0x00)		//Bit Set:Profiles are controlled by profile pins;only valid in Serial Mode.
#define		EN_MDU						((regBitVal_t)0x10)		//Bit Set:The Auxiliary Accumulator is used for Programmable Modulus.
#define		DIS_MDU					((regBitVal_t)0x00)		//Bit Set:The Auxiliary Accumulator is used for Linear Sweep Generation.

/*Bit Base Addresses In CFR2*/
#define		_PLL_LOCK_BA				ctrlFuncReg2.regByt1	//In Register Base Address:This read-only bit is set when the REF_CLK PLL is locked.
#define		_PLL_RESET_BA				ctrlFuncReg2.regByt1	//In Register Base Address:The PLL Logic is reset and non-operational until this bit is set.
#define		_VCO2_SEL_BA				ctrlFuncReg2.regByt1	//In Register Base Address:Choose this bit to optimize for power or performance.
#define		_PLL_DIV2_BA				ctrlFuncReg2.regByt1	//In Register Base Address:Choose the PLL Reference Frequency whether divided by 2 or not.
#define		_PLL_LO_RANGE_BA			ctrlFuncReg2.regByt1	//In Register Base Address:Choose the PLL LO Range.
#define		_PLL_PWRDWN_BA			ctrlFuncReg2.regByt1	//In Register Base Address:PLL Power-Down control bit.
#define		_XTAL_CLK_BA				ctrlFuncReg2.regByt1	//In Register Base Address:
#define		_CMOS_CLK_BA				ctrlFuncReg2.regByt1	//In Register Base Address:
#define		_PLL_MUL_FACTOR_BA		ctrlFuncReg2.regByt2	//In Register Base Address:PLL Multiplication Factor control.
#define		_PLL_OUT_DIV2_BA			ctrlFuncReg2.regByt2	//In Register Base Address:

/*Bit Offset Address In CFR2*/
#define		_PLL_LOCK_OFS				((regBitOfs_t)0x01)	//In Register Offset Address:This read-only bit is set when the REF_CLK PLL is locked.
#define		_PLL_RESET_OFS				((regBitOfs_t)0x02)	//In Register Offset Address:The PLL Logic is reset and non-operational until this bit is set.
#define		_VCO2_SEL_OFS				((regBitOfs_t)0x04)	//In Register Offset Address:Choose this bit to optimize for power or performance.
#define		_PLL_DIV2_OFS				((regBitOfs_t)0x08)	//In Register Offset Address:Choose the PLL Reference Frequency whether divided by 2 or not.
#define		_PLL_LO_RANGE_OFS			((regBitOfs_t)0x10)	//In Register Offset Address:Choose the PLL LO Range.
#define		_PLL_PWRDWN_OFS			((regBitOfs_t)0x20)	//In Register Offset Address:PLL Power-Down control bit.
#define		_XTAL_CLK_OFS				((regBitOfs_t)0x40)	//In Register Offset Address:Crystal Clock input control.
#define		_CMOS_CLK_OFS				((regBitOfs_t)0x80)	//In Register Offset Address:CMOS Clock input control.Ignored when XTAL Mode is enable.
#define		_PLL_MUL_FACTOR_OFS		((regBitOfs_t)0x7E)	//In Register Offset Address:PLL Multiplication Factor control.
#define		_PLL_OUT_DIV2_OFS			((regBitOfs_t)0x80)	//In Register Offset Address:

/*Bit Settings In CFR2*/
#define		EN_PLL_RESET				((regBitVal_t)0x00)		//Bit Set:The PLL Logic is reset and non-operational until this bit is disabled.
#define		DIS_PLL_RESET				((regBitVal_t)0x02)		//Bit Set:The PLL Logic operates normally.
#define		OPT_PERF_VCO2				((regBitVal_t)0x04)		//Bit Set:Use this setting to optimize for performance;this setting results in slightly higher power consumption.Note:When setting this bit, an IO_UPDATE must occur within 40us of the PLL Power-Down bit(CFR2[5])going low.
#define		OPT_PWR_VCO2				((regBitVal_t)0x00)		//Bit Set:Use this setting for VCO frequencies below 100MHz and/or to optimize for power rather than performance.
#define		EN_PLL_DIV2				((regBitVal_t)0x08)		//Bit Set:The PLL reference frequency =1/2 the REF_CLK input frequency.
#define		DIS_PLL_DIV2				((regBitVal_t)0x00)		//Bit Set:The PLL reference frequency = the REF_CLK input frequency.
#define		LOW_PLL_LO_RANGE			((regBitVal_t)0x10)		//Bit Set:Use this setting for PLL if the PLL reference frequency is < 5 MHz.
#define		HIGH_PLL_LO_RANGE			((regBitVal_t)0x00)		//Bit Set:Use this setting for PLL if the PLL feference frequency is > 5 MHz.
#define		EN_PLL_PWRDWN			((regBitVal_t)0x20)		//Bit Set:PLL is inactive and in its lowest power state.
#define		DIS_PLL_PWRDWN			((regBitVal_t)0x00)		//Bit Set:PLL is active.
#define		EN_XTAL_CLK				((regBitVal_t)0x40)		//Bit Set:Enable Crystal Clock input.
#define		DIS_XTAL_CLK				((regBitVal_t)0x00)		//Bit Set:Disable Crystal Clock input.
#define		EN_CMOS_CLK				((regBitVal_t)0x80)		//Bit Set:Enable CMOS Clock input.Ignored when XTAL Mode is enable.
#define		DIS_CMOS_CLK				((regBitVal_t)0x00)		//Bit Set:Disable CMOS Clock input.Ignored when XTAL Mode is enable.
#define		SHIFT_PLL_MUL_FACTOR		((regBitVal_t)0x01)		//Data Shift:NOTICE This is not a value for register.Use 'factor_Data<<SHIFT_PLL_MUL_FACTOR' to write in the register.
#define		EN_PLL_OUT_DIV2			((regBitVal_t)0x80)		//Bit Set:Enable PLL Output Frequency divided by 2.
#define		DIS_PLL_OUT_DIV2			((regBitVal_t)0x00)		//Bit Set:Disable PLL Output Frequency divided by 2.

/*Data Structure Defining*/
typedef uint8_t regByt_t;		//The data type of the element in the registers.
typedef uint8_t regBitVal_t;	//The data type of the bit value of the registers.
typedef uint8_t regBitOfs_t;	//The offset value type of the bits in the registers.
typedef uint8_t regAddr_t;	//The address type of each register.
typedef uint8_t inst_t;		//The instruction byte type.

typedef struct {				//Two word register type.
	regByt_t regByt1;
	regByt_t regByt2;
}word2_r;
typedef struct {				//Four word register type.
	regByt_t regByt1;
	regByt_t regByt2;
	regByt_t regByt3;
	regByt_t regByt4;
}word4_r;
typedef struct {				//Six word register type.
	regByt_t regByt1;
	regByt_t regByt2;
	regByt_t regByt3;
	regByt_t regByt4;
	regByt_t regByt5;
	regByt_t regByt6;
}word6_r;
typedef struct {				//Eight word register type.
	regByt_t regByt1;
	regByt_t regByt2;
	regByt_t regByt3;
	regByt_t regByt4;
	regByt_t regByt5;
	regByt_t regByt6;
	regByt_t regByt7;
	regByt_t regByt8;
} word8_r;

typedef struct {				//Main register structure of DDS
	word4_r ctrlFuncReg1;
	word2_r ctrlFuncReg2;
	word4_r dacReg;
	word4_r freqTurnWrd;
	word2_r phsOfsWrd;
	word8_r lsPara;
	word8_r lsDeltaPara;
	word4_r lsRampRate;
	word6_r profile0;
	word6_r profile1;
	word6_r profile2;
	word6_r profile3;
	word6_r profile4;
	word6_r profile5;
	word6_r profile6;
	word6_r profile7;
}ddsReg_t;
ddsReg_t ddsRegStruct;		//Global DDS register storage

typedef struct {				//Instruction byte setting structure
	int read:1;
	regAddr_t regAddr;
}instConfig_t;
instConfig_t instConfigStructure;

#endif		//#ifndef _DDS_REG_DEFINE
